Method of disposing dummy pattern

ABSTRACT

A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of disposing a dummy patternin a wiring process of a semiconductor integrated circuit having amultilevel wiring structure, the dummy patterns being used to planarizethe surface of a layer and the reduction of voltage noise among wires.

2. Background Information

In recent years, in order to increase the density and integration of asemiconductor integrated circuit, a multilevel wiring structure has beenadopted. In this multilevel wiring structure, wirings are arranged in aplurality of layers in a thickness direction of the semiconductorintegrated circuit. In such multilevel wiring structure, in order toprevent problems in the wirings, such as the breaking of wires, causedby concavity and convexity in each layer, the layers need to be madehighly planar. The most widely used method of planarizing a surface ofan interlayer insulation film formed on the wiring is a method using aCMP (chemical mechanical polishing) method. However, with respect tothis CMP method, if there is any deviation in the density of a wiringarrangement that is the foundation of the interlayer insulation film,i.e. if there are dense and non-dense portions in the wiring pattern,there is a possibility that some concavity and convexity will stillremain on the surface of the interlayer insulation film even after thepolishing, meaning that the surface of the interlayer insulation filmwill not be made completely planar. In order to resolve this problem, adummy pattern, i.e. an electrically floating metal piece, is arranged inthe non-dense portion of the wiring, and therefore the density of thewiring is made uniform.

For example, Japanese Laid Open Patent Application No. H10-335326(hereinafter to be referred to as Patent Reference 1), Japanese PatentApplication Laid Open No. H10-178013 (hereinafter to be referred to asPatent Reference 2), Japanese Laid Open Patent Application No.2000-277615 (hereinafter to be referred to as Patent Reference 3) andJapanese Laid Open Patent Application No. 2001-20327 (hereinafter to bereferred to as Patent Reference 4) disclose inventions relating to adummy pattern disposal.

According to the invention disclosed in Patent Reference 1, a lineardummy pattern is placed between two adjacent wirings and in parallelwith the wirings.

According to the invention disclosed in Patent Reference 2, a dummypattern separated from the wirings by a predetermined distance isdisposed so that a pattern density is made uniform by a pattern formingmethod including: a) a process of enlarging a wiring pattern by apredetermined measurement in terms of two dimension; b) a process ofgenerating a reversal pattern by reversing the enlarged wiring pattern;c) a process of superimposing a superimposing pattern and the reversalpattern and leaving only the region which is redundant between the twopatterns as a dummy metal pattern, the superimposing pattern having aplurality of same geometrical forms being arranged systematically atpredetermined intervals.

According to the invention disclosed in Patent Reference 3, a regionwhere the wirings are formed is divided into a number of blocks, amongwhich base dummy metal patterns with low metal density are formed in theblocks in the vicinity of the metal wiring and base dummy metal patternswith high metal density are formed in the blocks which are apart fromthe metal wiring.

According to the invention disclosed in Patent Reference 4, a dummypattern for adjusting the area ratio of a chip layout is formed on eachlayer while one dummy pattern has the same shape as of the dummypatterns in other layers and overlaps the other dummy patterns formed inother layers. Furthermore, by having the dummy pattern in each layerconnected to either the power supply wiring (hereinafter to be referredto as a VDD wiring) or the ground wiring (hereinafter to be referred toas a GND wiring), a power source capacity for decreasing radiant noisecaused by an instantaneous current of the semiconductor integratedcircuit is configured.

In order to make the wiring density uniform, it is desirable that thedummy patterns are disposed as evenly as possible in the free spacesamong the wires. However, disposing the dummy patterns without anyrestriction might result in causing unnecessary capacitive connectionsamong different wirings, which can induce problems such as changing thecircuit characteristics, increasing the parasitic capacitance to causesignal delay, etc. Therefore, in disposing the dummy patterns, it isnecessary to give consideration to the influences of possible changes inthe parasitic capacitance and voltage noise which are accompanied by thedummy pattern disposal, in addition to making the pattern densityuniform.

In accordance with the inventions of Patent References 1 to 3, apossible increase in the parasitic capacitance accompanied by the dummypattern disposal is controlled by adjusting the disposing intervals orthe pattern, etc. of the dummy patterns, but no direct consideration isgiven to the influences of possible voltage noise generated among wiresin disposing the dummy pattern. Accordingly, with respect to these priorart inventions, there is a possibility that those wires which arenormally not affected by the voltage noise might be affected by thevoltage noise due to disposing the dummy patterns.

According to the invention disclosed in Patent Reference 4, the powersource capacity is configured in order to decrease the radiant noisecaused by the instantaneous current of the semiconductor integratedcircuit. The invention does not give consideration to disposing thedummy patterns considering the influences of possible voltage noisegenerated among wires in disposing the dummy pattern.

In view of the above, it will be apparent to those skilled in the artfrom this disclosure that there exists a need for an improved method ofdisposing dummy pattern in a semiconductor integrated circuit. Thisinvention addresses this need in the art as well as other needs, whichwill become apparent to those skilled in the art from this disclosure.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to resolve theabove-described problems, and to provide an improved method of disposingdummy pattern in a semiconductor integrated circuit.

In accordance with one aspect of the present invention, a method ofdisposing a dummy pattern, which is used for a semiconductor integratedcircuit having a multilevel wiring structure, includes the steps of:obtaining a first inter-wiring parasitic capacity and a first wiringtotal parasitic capacity for each wiring using wiring layout data of thesemiconductor integrated circuit and initial dummy pattern layout data;creating a first inter-wiring parasitic capacity data base based on thefirst inter-wiring parasitic capacity; creating a first wiring totalparasitic capacity data base based on the first wiring total parasiticcapacity; performing a first dynamic simulation for identifying a firstwiring which should be affected by a voltage noise using the firstinter-wiring parasitic capacity data base and a first wiring totalparasitic capacity data base; performing a first static simulation foridentifying a second wiring which should be affected by a voltage noiseusing the first inter-wiring parasitic capacity data base and the firstwiring total parasitic capacity data base; creating a first wiringinformation data base storing the results of the first dynamicsimulation and the first static simulation, the result of the firstdynamic simulation being information about the first wiring, and theresult of the first static simulation being information about the secondwiring; and performing an additional insertion of dummy pattern near athird wiring in the initial dummy pattern, the third wiring beingdetermined as a wiring which should be affected by a voltage noise basedon the first wiring information data base.

In accordance with another aspect of the present invention, a method ofdisposing a dummy pattern, which is used for a semiconductor integratedcircuit having a multilevel wiring structure in which a power supplywiring layer and a signal wiring layer are sequentially laminated,includes the step of: disposing a dummy pattern on a region of thesignal wiring layer that is adjacent to the power supply wiring layer,the power supply wiring layer including a first power supply wiringlayer having a first power supply wiring extending toward a firstdirection, and a second power supply wiring layer having a second powersupply wiring extending toward a second direction which is perpendicularwith the first direction, the region corresponding to the crossoverpoint where the first power supply wiring and the second power supplywiring cross over each other.

These and other objects, features, aspects, and advantages of thepresent invention will become apparent to those skilled in the art fromthe following detailed description, which, taken in conjunction with theannexed drawings, discloses preferred embodiments of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the attached drawings which form a part of thisoriginal disclosure:

FIG. 1 is a flow chart showing an example of a layout process of asemiconductor integrated circuit using a dummy pattern disposing methodaccording to first and second embodiments of the present invention;

FIG. 2 is a flow chart showing a detailed process flow of a dummypattern additional disposing process in the first and second embodimentsof the present invention;

FIG. 3 is a simplified model diagram for explaining an influence of avoltage noise;

FIG. 4 is a flow chart showing a detailed process flow of a dummypattern insertion process in the first embodiment of the presentinvention;

FIG. 5 is a diagram for explaining a physical relationship between awiring which could be affected by a voltage noise and a wiring whichimparts voltage noise in the first embodiment of the present invention;

FIG. 6 is a diagram for explaining a physical relationship between awiring which could be affected by a voltage noise, a wiring whichimparts voltage noise and a wiring which is capable of receiving avoltage noise in the first embodiment of the present invention;

FIG. 7 is a diagram for explaining a dummy pattern disposal according tothe first embodiment of the present invention;

FIGS. 8A and 8B are diagrams for explaining possible changes in theparasitic capacitance in the first embodiment of the present invention;

FIG. 9 is a table for showing a result of a simulation according to thefirst embodiment of the present invention;

FIG. 10 is a flow chart showing a detailed process flow of a dummypattern insertion process in the second embodiment of the presentinvention;

FIG. 11 is a diagram for explaining a physical relationship between awiring which could be affected by a voltage noise and a wiring whichimparts voltage noise in the second embodiment of the present invention;

FIG. 12 is a diagram for explaining a physical relationship between awiring which could be affected by a voltage noise, a wiring whichimparts voltage noise and a wiring which is capable of receiving avoltage noise in the second embodiment of the present invention;

FIG. 13 is a diagram for explaining a dummy pattern disposal accordingto the second embodiment of the present invention;

FIGS. 14A and 14B are diagrams for explaining possible changes in theparasitic capacitance in the second embodiment of the present invention;

FIG. 15 is a flow chart showing an example of a layout process of asemiconductor integrated circuit using a dummy pattern disposing methodaccording to a third embodiment of the present invention;

FIG. 16 is a flow chart showing a detailed process flow of a dummypattern deleting/additional disposing process in the third embodiment ofthe present invention; and

FIGS. 17A and 17B are diagrams showing a portion of a wire structure ina semiconductor integrated circuit using a dummy pattern disposingmethod according to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Selected embodiments of the present invention will now be explained withreference to the drawings. It will be apparent to those skilled in theart from this disclosure that the following descriptions of theembodiments of the present invention are provided for illustration onlyand not for the purpose of limiting the invention as defined by theappended claims and their equivalents.

Referring now to the drawings, preferred embodiments of the presentinvention will be described in detail.

First Embodiment

FIG. 1 is a flow chart showing an example of a layout process of asemiconductor integrated circuit using a dummy pattern disposing methodaccording to a first embodiment of the present invention. The layoutprocess of FIG. 1 includes a wiring process S100, an initial dummypattern disposing process S200, a dummy pattern additional disposingprocess S300, a mask verification process S400 and a mask processingprocess S500. The dummy pattern disposing method of the presentinvention is executed at the additional dummy pattern disposing processS300, and it will be described in more detail below.

In the wiring process S100, various functional blocks that are theconstituents of the semiconductor integrated circuit are disposed atpredetermined positions and are mutually connected to each other bywiring layers. In addition, in the wiring process S100, capacityextraction is performed with respect to each wire, and using the resultof the capacity extraction, a post layout simulation, i.e. dynamicsimulation, static simulation etc., is performed. In the initial dummypattern disposing process S200, dummy metal patterns are arranged infree spaces of the wiring layout for the purpose of adjusting the wiringpattern density. The arrangement of dummy metal patterns can be done byperforming logic operations as are done in the conventional method. Forinstance, first, one can enlarge the wiring pattern of the semiconductorintegrated circuit by a predetermined measurement, then calculate areversal region which is formed by a region excluding the enlargedwiring pattern, and perform logic operation processing such that thedummy metal patterns are arranged in the reversal region. Thisarrangement of dummy metal patterns can also be done manually. The maskverification process S400 and the mask processing process S500 are donein the same way as in the conventional method, and since they do notdirectly relate to the invention itself, explanations thereof will beomitted here.

Next, the additional dummy pattern disposing process S300, in which thedummy pattern disposing method of the present invention is implemented,will be explained. FIG. 2 is a flow chart showing a process flow of theadditional dummy pattern disposing process S300.

In step S301, layout data, i.e. wiring pattern data and initial dummymetal pattern data, generated in the wiring process S100 and the initialdummy pattern disposing process S200 is used to extract a parasiticcapacity with respect to each wiring. The parasitic capacity extractedhere includes inter-wiring parasitic capacities and a wiring totalparasitic capacity. The inter-wiring parasitic capacity is a parasiticcapacity generated between adjacent wirings, and the wiring totalparasitic capacity is derived by adding a substrate capacity generatedbetween the wiring and the semiconductor substrate to the inter-wiringparasitic capacity. On the basis of the inter-wiring parasiticcapacities and the wiring total parasitic capacity extracted in stepS301, inter-wiring parasitic capacity data base DB1 and wiring totalparasitic capacity data base DB2 are generated. These data bases storeinformation, for instance, about a node name of the wiring, a parasiticcapacity with respect to that node and so forth.

In step S302, a dynamic simulation for identifying the wirings whichcould be affected by voltage noise is performed using the inter-wiringparasitic capacity data base DB1 (first inter-wiring parasitic capacitydata base) and the wiring total parasitic capacity data base DB2 (firstwiring total parasitic capacity data base). In this dynamic simulation,several test patterns TP are used to virtually operate the circuit andcalculate dynamically the amount of voltage noise that each wiringimparts to the adjacent wirings. Then those wirings that may malfunctiondue to such voltage noise, i.e. those wirings having a possibility ofreceiving voltage noise with a level surpassing a predetermined basis,are identified as the wirings which could be affected by voltage noise.Now, a specific method of identifying the wirings which could beaffected by voltage noise will be described using a two dimensionalsimple model made up of wiring 1 and wiring 2 as shown in FIG. 3. InFIG. 3, provided that the inter-wiring parasitic capacity between wiring1 and wiring 2 is defined as Cw, the substrate capacity between wiring 2and the semiconductor substrate (GND) is defined as Cs, and the signalvoltage passing through wiring 1 is defined as Vs, the amount of voltagenoise Vn that wiring 1 can give to wiring 2 can be defined asVn=Vs×Cw/(Cw+Cs). As to a judging standard whether wiring 2 maymalfunction due to voltage noise, for instance, by assuming that theamount of voltage noise Vn surpasses the threshold voltage Vth of thetransistor connected to the wiring 2, it will be possible tospecifically identify the wiring which could be affected by voltagenoise. The judging standard does not necessarily have to be based on thecomparison between the amount of voltage noise Vn and the thresholdvoltage Vth of the transistor, and it is also possible to set differentjudging standard as appropriate. Furthermore, in identifying the wiringswhich could be affected by voltage noise, the amount of noise receivedfrom the adjacent wirings in the three dimensional direction, i.e. thevertical direction, is considered in addition to the amount of noisereceived from the wirings located in the same layer as shown in FIG. 3.Then on the basis of the results of the dynamic simulation and thestatic simulation, which will be described below, wiring informationdata base DB3 containing information about the wirings which maymalfunction in response to voltage noise is produced. This wiringinformation data base DB3 stores a node name, amount of voltage noise,etc. of the wirings which may malfunction due to voltage noise.

In step S303, a static simulation for identifying the wirings whichcould be affected by voltage noise is performed using the inter-wiringparasitic capacity data base DB1 and the wiring total parasitic capacitydata base DB2. In this static simulation, the amount of voltage noisethat each wiring imparts to the adjacent wirings is calculatedstatically without using any test pattern. Then those wirings which maymalfunction due to such voltage noise, i.e. those wirings having apossibility of receiving voltage noise with a level surpassing apredetermined basis, are identified as the wirings which could beaffected by voltage noise. As to a specific method of identifying thewirings which could be affected by voltage noise, it is the same as thecase of the dynamic simulation described with reference to FIG. 3. Thenas mentioned before, on the basis of the results of the dynamicsimulation and the static simulation, wiring information data base DB3containing information about the wirings which may malfunction inresponse to voltage noise is produced. This wiring information data baseDB3 stores a node name, amount of voltage noise, etc. of the wiringswhich could become malfunctional due to voltage noise.

In step S600, on the basis of the wiring information data base DB3generated through the dynamic simulation and the static simulation,additional insertion of dummy patterns considering the influence ofvoltage noise is performed by a certain method which will be describedbelow.

This is the overall flow of the additional dummy pattern disposingprocess S300.

Next, details of a dummy pattern insertion process S600 will bedescribed. FIG. 4 is a flow chart showing a process flow of the dummypattern insertion process S600.

In step S601, analysis of the wiring structure is done using the wiringinformation data base DB3. In the structure analysis of the firstembodiment, for instance, if the wiring information data base DB3 storesinformation about wiring (A) as the wiring which may malfunction inresponse to voltage noise, a wiring structure, as shown in FIG. 5, wherewiring (B) 4, which imparts voltage noise to wiring (A) 3, exists aboveand/or below wiring (A) 3 will be extracted. The structure analysis herecan be a visual analysis using the actual layout data, however, it doesnot necessarily have to be a visual analysis.

In step S602, for instance, it is to be determined whether there areadjacent wirings in the same layer of wiring (A) 3 shown in FIG. 5. Anadjacent wiring in this case, is defined as a wiring which is located inthe vicinity of wiring (A) 3, and which is apart from wiring (A) 3 by adistance that is sufficient for a dummy pattern to be disposed. Whenthere is an adjacent wiring in the same layer of wiring (A) 3 in stepS602, then step S603 is to be executed. On the other hand, when there isno adjacent wiring in the same layer of wiring (A) 3 in step S602, thenstep S605 is to be executed.

In step S603, for instance, when adjacent wiring (C) 5 exists in thesame layer of wiring (A) 3 as shown in FIG. 6, it is to be determinedwhether adjacent wiring (C) 5 is capable of receiving voltage noise.Here, the wiring which is capable of receiving voltage noise, forinstance, is a VDD wiring and a GND wiring, etc. If adjacent wiring (C)5 is a wiring which should not receive voltage noise, i.e. if it is asignal wiring etc., the dummy pattern insertion process S600 shouldterminate without additionally inserting any dummy pattern betweenwiring (A) 3 and adjacent wiring (C) 5. On the other hand, if adjacentwiring (C) 5 is a wiring which is capable of receiving voltage noise,step S604 is to be executed.

In step S604, for instance, dummy patterns 6 are inserted additionallybetween wiring (A) 3 and adjacent wiring (C) 5 as shown in FIG. 7. Theinterval between the dummy patterns 6 and wiring (A) 3 or adjacentwiring (C) 5 should be appropriate if it is over the minimum intervalvalue of wirings specified by the layout rules. Likewise, the size ofthe dummy pattern 6 should be appropriate if it is over the minimum sizemeasurement of wirings specified by the layout rules.

In step S605, since there is no adjacent wiring in the same layer ofwiring (A) 3, adjacent wiring (C) 5, which is capable of receivingvoltage noise, is inserted in the same layer of wiring (A) 3 and dummypatterns 6 are additionally inserted between wiring (A) 3 and adjacentwiring (C) 5, as shown in FIG. 7, for instance. The interval between thedummy patterns 6 and wiring (A) 3 or adjacent wiring (C) 5 should beappropriate if it is over the minimum interval value of wiringsspecified by the layout rules. Likewise, the size of the dummy pattern 6should be appropriate if it is over the minimum size measurement ofwirings specified by the layout rules.

This is the overall flow of the dummy pattern insertion process S600.

Next, with reference to FIGS. 8A and 8B, the effects of dummy patterninsertion according to the first embodiment of the present inventionwill be described.

FIG. 8A shows the parasitic capacities generated between wirings whendummy patterns 6 are not disposed between wiring (A) 3, which receivesvoltage noise, and adjacent wiring (C) 5 positioned in the same layer.Here, in order to make the description simple, it is assumed that wiring(B) 4 which imparts voltage noise to wiring (A) 3 is located only in thelower layer below wiring (A) 3. In FIG. 8A, Cab1 and Cab3 are parasiticcapacities generated between the side faces of wiring (A) 3 and the sidefaces of wiring (B) 4, respectively, and Cab2 is a parasitic capacitygenerated between the bottom surface of wiring (C) 3 and the uppersurface of wiring (B) 4. C_(AC) is a total parasitic capacity generatedbetween wiring (A) 3 and adjacent wiring (C) 5. Here, assuming that asignal voltage passing through wiring (B) 4 is Vb, the amount of voltagenoise Vn which wiring (B) 4 imparts to wiring (A) 3 can be derived fromFormula (1)

Vn=Vbx(Cab1+Cab2+Cab3)/(Cab1+Cab2+Cab3+C _(AC))  (1)

FIG. 8B shows the parasitic capacities generated between wirings whendummy patterns 6 are disposed between wiring (A) 3, which receivesvoltage noise, and adjacent wiring (C) 5 positioned in the same layer.Here, in order to make the description simple, it is assumed that wiring(B) 4 which imparts voltage noise to wiring (A) 3 is located only in thelower layer below wiring (A) 3. In FIG. 8B, Cab1′ and Cab3′ areparasitic capacities generated between the side faces of wiring (A) 3and the side faces of wiring (B) 4, respectively, and Cab2′ is aparasitic capacity generated between the bottom surface of wiring (A) 3and the upper surface of wiring (B) 4. C_(AC)′ is a total parasiticcapacity generated between wiring (A) 3 and adjacent wiring (C) 5through the dummy patterns 6. Here, considering that a signal voltagepassing through wiring (B) 4 is Vb, the amount of voltage noise Vn′which wiring (B) 4 imparts to wiring (A) 3 can be derived from Formula(2).

Vn′=Vbx(Cab1′+Cab2′+Cab3′)/(Cab1′+Cab2′+Cab3′+C _(AC)′)  (2)

Here, due to having the dummy patterns 6 disposed, a portion of theparasitic capacities Cab1, Cab2 and Cab3 (FIG. 8A) generated betweenwiring (A) 3 and wiring (b) 4 might be distributed to the side ofadjacent wiring (C) 5, which results in some increase/decrease in thecapacity value. However, such fluctuation is so small that it can beconsidered as almost zero. Therefore, it can be considered thatCab1′≈Cab1, Cab2′≈Cab2, Cab3′ Cab3. On the other hand, since theeffective interval between wiring (A) 3 and adjacent wiring (C) 5becomes smaller due to having the dummy patterns 6 disposed, the totalparasitic capacity C_(AC)′ (FIG. 8B) becomes larger than the totalparasitic capacity C_(AC) (FIG. 8A) generated between wiring (A) 3 andadjacent wiring (C) 5 (i.e. C_(AC)′>C_(AC)). At this time, under theconditions of (Cab1′+Cab2′Cab3′)/(Cab1+Cab2+Cab3)<<(C_(AC)′/C_(AC)),C_(AC)′>C_(AC), the condition Vn′<Vn will be realized between Formula(1) and Formula (2). Accordingly, by having the dummy patterns 6disposed between wiring (A) 3, which receives voltage noise, andadjacent wiring (C) 5, which is positioned in the same layer, it ispossible to decrease the amount of voltage noise that wiring (A) 3 issupposed to receive from wiring (B) 4.

FIG. 9 is a chart showing the amount of voltage noise that wiring (A) 3receives from wiring (B) 4, with respect to the structures of FIG. 8Aand FIG. 8B, respectively, the amount of voltage noise that wiring (A) 3receives from wiring (B) 4 being derived as a result of a simulation.

In FIG. 9, an A-B inter-wiring total parasitic capacitance C_(AB)corresponds to Cab1+Cab2+Cab3 in FIG. 8A and to Cab1′+Cab2′+Cab3′ inFIG. 8B. An A-C inter-wiring total parasitic capacitance C_(AC)corresponds to C_(AC) in FIG. 8A and to C_(AC)′ in FIG. 8B. A totalparasitic capacitance C_(TOTAL) is a total amount derived by adding upthe A-B inter-wiring total capacitance C_(AB) and the A-C inter-wiringtotal parasitic capacitance C_(AC) and the substrate capacitance C_(S)generated between each wiring and the semiconductor substrate. Nowassuming that the signal voltage passing through wiring (B) 4 is Vb, theamount of voltage noise Vn (Vn′) which wiring (A) 3 receives from wiring(B) 4 can be acquired by Formula (3). In this simulation, the signalvoltage Vb passing through wiring (B) 4 is assumed as 1.0 V, forexample.

Vn=Vb×C _(AB)/(C _(AB) +C _(AC)+containership)  (3)

Referring to FIG. 9, it is clear that by having the dummy patterns 6disposed between wiring (A) 3, which receives voltage noise, andadjacent wiring (C) 5 positioned in the same layer, the A-B inter-wiringtotal capacitance C_(AB) hardly changes while the A-C inter-wiring totalparasitic capacitance C_(AC) increases. By this arrangement, the amountof voltage noise Vn that wiring (A) 3 receives from wiring (B) 4 can bedecreased by approximately 54%.

In the dummy pattern disposing method according to the first embodimentof the present invention, those wirings which could be affected byvoltage noise are identified by first extracting a parasitic capacitancewith respect to each wiring, and then executing the dynamic and staticsimulations using the parasitic capacitance to calculate the amount ofvoltage noise that each wiring imparts to its adjacent wiring. Then,considering the structure in which the wiring which imparts voltagenoise (e.g. wiring (B) 4 in FIG. 5) is located above and/or below thewiring which is identified as one which may malfunction by receivingvoltage noise (e.g. wiring (A) 3 in FIG. 5), by disposing the dummypatterns 6 between wiring (A) 3 and the wiring which is capable ofreceiving voltage noise (e.g. adjacent wiring (C) 5 in FIG. 6) locatedin the same layer of wiring (A) 3, it is possible to increase theparasitic capacitance between wiring (A) 3, which receives voltagenoise, and adjacent wiring (C) 5, which is capable of receiving voltagenoise. By this arrangement, it is possible to decrease the amount ofvoltage noise that the wiring, which may malfunction due to voltagenoise, receives, and prevent possible malfunction of the semiconductorintegrated circuit caused by voltage noise.

Second Embodiment

In this embodiment, a layout process of a semiconductor integratedcircuit using a dummy pattern disposing method is the same as the layoutprocess shown in FIG. 1 in the first embodiment of the presentinvention. Also, with respect to a dummy pattern disposing process inthis embodiment, a basic flow is the same as the dummy pattern disposingprocess shown in FIG. 2 in the first embodiment of the presentinvention. In addition, in this embodiment, in the dummy patternadditional disposing process S300 shown in FIG. 2, a dummy patterninsertion process S700 (which will be described below) is implementedinstead of the dummy pattern insertion process S600 in the firstembodiment. In the following, the details of the dummy pattern insertionprocess S700 will be described.

FIG. 10 is a flow chart showing a detailed process flow of the dummypattern insertion process S700.

In step S701, analysis of the wiring structure is done using the wiringinformation data base DB3. In the structure analysis of the secondembodiment, for instance, if the wiring information data base DB3 storesinformation about wiring (A) as one which may malfunction in response tovoltage noise, a wiring structure, as shown in FIG. 11, where wiring (B)8, which imparts voltage noise to wiring (A) 7, exists in parallel withone or both sides of the wiring (A) 7 in the same layer of wiring (A) 7will be extracted. The structure analysis here can be visual analysisusing actual layout data, however, it does not necessarily have to be avisual analysis.

In step S702, for instance, it is to be determined whether there areadjacent wirings above and/or below wiring (A) 7 shown in FIG. 11. Whenthere is an adjacent wiring above and/or below wiring (A) 7 in stepS702, then step S703 is to be executed. On the other hand, when there isno adjacent wiring above and below wiring (A) 7 in step S702, then stepS705 is to be executed.

In step S703, for instance, when adjacent wiring (C) 9 exists aboveand/or below wiring (A) 7 as shown in FIG. 12, it is to be determinedwhether adjacent wiring (C) 9 is capable of receiving voltage noise.Here, the wiring which is capable of receiving voltage noise, forinstance, is a VDD wiring and a GND wiring, etc. If adjacent wiring (C)9 is wiring which should not receive voltage noise, i.e. if it is asignal wiring etc., the dummy pattern insertion process S700 shouldterminate without additionally inserting any dummy pattern betweenwiring (A) 7 and adjacent wiring (C) 9. On the other hand, if adjacentwiring (C) 9 is a wiring which is capable of receiving voltage noise,step S704 is to be executed.

In step S704, for instance, a wiring layer is inserted between the layerwhere wiring (A) 7 is formed and the layer where wiring (C) 9 disposedbelow wiring (A) 7 is formed, and a dummy pattern 10 is additionallyformed on the inserted wiring layer so that it is inserted betweenwiring (A) 7 and wiring (C) 9 as shown in FIG. 13. The size of the dummypattern 10 should be appropriate if it is over the minimum sizemeasurement of wirings specified by the layout rules.

In step S705, since there is no adjacent wiring above and/or belowwiring (A) 7, adjacent wiring (C) 9, which is capable of receivingvoltage noise, is inserted in the below layer of wiring (A) 7, and aftera wiring layer is inserted between the layer where wiring (A) 7 isformed and the layer where the wiring (C) 9 is formed, a dummy pattern10 is additionally formed on the inserted wiring layer so that it isinserted between wiring (A) 7 and wiring (C) 9, as shown in FIG. 13, forinstance. The size of the dummy pattern 10 should be appropriate if itis over the minimum size measurement of wirings specified by the layoutrules.

This is the overall flow of the dummy pattern insertion process S700.

Next, with reference to FIGS. 14A and 14B, the effects of dummy patterninsertion according to the second embodiment of the present inventionwill be described.

FIG. 14A shows the parasitic capacities generated between wirings whendummy patterns 10 are not disposed between wiring (A) 7, which receivesvoltage noise, and adjacent wiring (C) 9 positioned in the lower layerbelow wiring (A) 7. Here, in order to make the description simple, it isassumed that wiring (B) 8 which imparts voltage noise to wiring (A) 7 islocated at only one side of wiring (A) 7 in the same layer. In FIG. 8A,Cac1 and Cac3 are parasitic capacities generated between the side facesof wiring (A) 7 and adjacent wiring (C) 9, respectively, and Cac2 is aparasitic capacity generated between the bottom surface of wiring (A) 7and adjacent wiring (C) 9. C_(AB) is a total parasitic capacitygenerated between wiring (A) 7 and wiring (B) 8. Here, assuming that asignal voltage passing through wiring (B) 8 is Vb, the amount of voltagenoise Vn which wiring (B) 8 imparts to wiring (A) 7 can be derived fromFormula (4)

Vn=Vb×C _(AB)/(Cac1+Cac2+Cac3+C _(AB))  (4)

FIG. 14B shows the parasitic capacities generated between wirings whendummy patterns 10 are disposed between wiring (A) 7, which receivesvoltage noise, and adjacent wiring (C) 9 positioned in the lower layerbelow wiring (A) 7. Here, in order to make the description simple, it isassumed that wiring (B) 8 which imparts voltage noise to wiring (A) 7 islocated at only one side of wiring (A) 7 in the same layer. In FIG. 14B,Cac1′ and Cac3′ are parasitic capacities generated between the sidefaces of wiring (A) 7 and adjacent wiring (C) 9 through the dummypattern 10, respectively, and Cac2′ is a parasitic capacity generatedbetween the bottom surface of wiring (A) 7 and the upper surface ofadjacent wiring (C) 9. C_(AB)′ is a total parasitic capacity generatedbetween wiring (A) 7 and wiring (B) 8. Here, considering that a signalvoltage passing through wiring (B) 8 is Vb, the amount of voltage noiseVn′ which wiring (B) 8 imparts to wiring (A) 7 can be derived fromFormula (5).

Vn′=Vb×C _(AB)′/(Cac1′+Cac2′+Cac3′+C _(AB)′)  (5)

Here, due to having the dummy pattern 10 disposed, a portion of thetotal parasitic capacity C_(AB) (FIG. 14A) generated between wiring (A)7 and wiring (B) 8 might be distributed to the side of adjacent wiring(C) 9 in the lower layer below the wiring (A) 7. Therefore, the totalparasitic capacity C_(AB)′ (FIG. 14B) becomes smaller than the totalparasitic capacity C_(AB) (FIG. 14A) generated between wiring (A) 7 andwiring (B) 8 (i.e. C_(AB)′<C_(AB)). On the other hand, since theeffective interval between wiring (A) 7 and adjacent wiring (C) 9located in the lower layer below wiring (A) 7 becomes smaller due tohaving the dummy pattern 10 disposed, the parasitic capacities Cac1′,Cac2′ and Cac3′ (FIG. 14B) become larger than the parasitic capacitiesCac1, Cac2 and Cac3 (FIG. 14A) generated between wiring (A) 7 andadjacent wiring (C) 9 (i.e. Cac1′>Cac1, Cac2′>Cac2, Cac3′>Cac3).Thereby, under the conditions of (Cac1′+Cac2′+Cac3′)>(Cac1+Cac2+Cac3),C_(AB)′<C_(AB), a condition as Vn′<Vn will be realized between Formula(4) and (5). Accordingly, by having the dummy pattern 10 disposedbetween wiring (A) 7, which receives voltage noise, and adjacent wiring(C) 9, which is positioned in the lower layer below wiring (A) 7, it ispossible to decrease the amount of voltage noise that wiring (A) 7 issupposed to receive from wiring (B) 8.

In the dummy pattern disposing method according to the second embodimentof the present invention, those wirings which could be affected byvoltage noise are identified by first extracting a parasitic capacitancewith respect to each wiring, and then executing the dynamic and staticsimulations using the parasitic capacitance to calculate the amount ofvoltage noise that each wiring imparts to its adjacent wiring. Then,considering the structure in which the wiring which imparts voltagenoise (e.g. wiring (B) 8 in FIG. 11) is located in the same layer and inparallel with the wiring which is identified as one which maymalfunction by receiving voltage noise (e.g. wiring (A). 7 in FIG. 11),by disposing the dummy patterns 10 between wiring (A) 7 and the wiringwhich is capable of receiving voltage noise (e.g. adjacent wiring (C) 9in FIG. 12) located above and/or below wiring (A) 7, it is possible todecrease the parasitic capacitance between wiring (A) 7, which receivedvoltage noise, and wiring (B) 8, which imparts voltage noise. By thisarrangement, it is possible to decrease the amount of voltage noise thatthe wiring, which may malfunction due to voltage noise, receives, andprevent possible malfunction of the semiconductor integrated circuitcaused by voltage noise.

Third Embodiment

FIG. 15 is a flow chart showing an example of a layout process of asemiconductor integrated circuit using a dummy pattern disposing methodaccording to a third embodiment of the present invention. In addition,in this embodiment, in this embodiment, instead of the dummy patternadditional insertion process S300 in the dummy pattern disposing methodin the first and second embodiments shown in FIG. 1, a dummy patterndeleting/additional disposing process S800 (which will be describedbelow) is implemented. The rest of the structure of the layout processaccording to the third embodiment of the present invention is the sameas the first or second embodiment, and as for the structure elementsthat are the same as the first and second embodiments, the samereference numbers will be used, and redundant explanation of thosestructure elements will be omitted. In the following, details of thedummy pattern insertion process S700 will be described.

FIG. 16 is a flow chart showing a detailed process flow of the dummypattern deleting/additional disposing process S800.

In step S801, layout data, i.e. wiring pattern data and initial dummymetal pattern data, generated in the wiring process S100 (FIG. 1) andthe initial dummy pattern disposing process S200 (FIG. 2) is used toextract a parasitic capacity with respect to each wiring. The parasiticcapacity extracted here includes inter-wiring parasitic capacities and awiring total parasitic capacity. The inter-wiring parasitic capacity isa parasitic capacity generated between adjacent wirings, and the wiringtotal parasitic capacity is derived by adding a substrate capacitygenerated between the wiring and the semiconductor substrate to theinter-wiring parasitic capacity. On the basis of the inter-wiringparasitic capacities and the wiring total parasitic capacity extractedin step S801, inter-wiring parasitic capacity data base DB4 and wiringtotal parasitic capacity data base DB5 are generated. These data basesstore information, for instance, about a node name of the wiring, aparasitic capacity with respect to that node and so forth.

In step S802, a dynamic simulation for identifying the wirings whichcould be affected by voltage noise is performed using the inter-wiringparasitic capacity data base DB4 (first inter-wiring parasitic capacitydata base) and the wiring total parasitic capacity data base DB5 (firstwiring total parasitic capacity data base). In this dynamic simulation,several test patterns TP are used to virtually operate the circuit andcalculate dynamically the amount of voltage noise that each wiringimparts to the adjacent wirings. Then those wirings which maymalfunction due to such voltage noise, i.e. those wirings having apossibility of receiving voltage noise with a level surpassing apredetermined basis, are identified as the wirings which could beaffected by voltage noise. As to a judging standard for identifying awiring which is capable of receiving voltage noise, as in the case ofthe first embodiment, by assuming that the amount of voltage noisesurpasses the threshold voltage Vth of the transistor connected to awiring, it will be possible to specifically identify the wiring whichcould be affected by voltage noise. The judging standard does notnecessarily have to be based on the comparison between the amount ofvoltage noise Vn and the threshold voltage Vth of the transistor, and itis also possible to set different judging standard as appropriate. Thenon the basis of the results of the dynamic simulation and the staticsimulation, which will be described below, wiring information data baseDB6 containing information about the wirings which may malfunction inresponse to voltage noise is produced. This wiring information data baseDB6 stores a node name, amount of voltage noise, etc. of the wiringswhich may malfunction due to voltage noise.

In step S803, a static simulation for identifying the wirings whichcould be affected by voltage noise is performed using the inter-wiringparasitic capacity data base DB4 and the wiring total parasitic capacitydata base DB5. In this static simulation, the amount of voltage noisethat each wiring imparts to the adjacent wirings is calculatedstatically without using any test pattern. Then those wirings which maymalfunction due to such voltage noise, i.e. those wirings having apossibility of receiving voltage noise with a level surpassing apredetermined basis, are identified as the wirings which could beaffected by voltage noise. As to a specific method of identifying thewirings which could be affected by voltage noise, it is the same as thecase of the dynamic simulation. Then as mentioned before, on the basisof the results of the dynamic simulation and the static simulation,wiring information data base DB6 containing information about thewirings which may malfunction in response to voltage noise is produced.This wiring information data base DB6 stores a node name, amount ofvoltage noise, etc. of the wirings which may malfunction due to voltagenoise.

In step S804, on the basis of the wiring information data base DB6generated through the dynamic simulation and the static simulation, itis to be determined whether there are wirings which could be affected byvoltage noise. If there is no wiring which could be affected by voltagenoise, i.e. if the wiring information data base DB6 does not storeinformation of wirings which may malfunction due to voltage noise, thedummy pattern deleting/additionally disposing process S800 shouldterminate. On the other hand, if there is a wiring which could beaffected by voltage noise, i.e. if the wiring information data base DB6has information of wiring which may malfunction due to voltage noise(hereinafter to be referred to as error information), the dummy patterndeleting/additionally disposing process S800 is to be executed.

In step S805, with respect to the wiring of which error information isstored in the wiring information data base DB6, i.e. with respect to thewiring which could be affected by voltage noise, a process of deletingan initial dummy pattern which adjoins this wiring or downsizing theinitial dummy pattern is to be executed.

In step S806, parasitic capacities, i.e. inter-wiring parasiticcapacities and a wiring total parasitic capacity with respect to eachwiring are extracted again using the layout data of which the initialdummy pattern which adjoins the wiring, which could be affected byvoltage noise, is deleted or downsized. Then, on the basis of theinter-wiring parasitic capacities and the wiring total parasiticcapacity extracted in step S806, inter-wiring parasitic capacity database DB7 and wiring total parasitic capacity data base DB8 aregenerated. These data bases store information, for instance, about anode name of the wiring, a parasitic capacity with respect to that node,and so forth.

In step S807, in order to confirm the results of step S805 which is donewith respect to the wiring which could be affected by voltage noise,i.e. the results of deleting or downsizing the initial dummy patternwhich adjoins the wiring which could be affected voltage noise, adynamic simulation is performed again using the inter-wiring parasiticcapacity data base DB7 and the wiring total parasitic capacity data baseDB8. In this dynamic simulation, as in the case of the dynamicsimulation in step S802, several test patterns TP are used to virtuallyoperate the circuit and calculate dynamically the amount of voltagenoise that each wiring imparts to the adjacent wirings. Then on thebasis of the results of the dynamic simulation and the staticsimulation, which will be described below, wiring information data baseDB9 is produced. This wiring information data base DB9 stores a nodename, amount of voltage noise, etc. of the wirings which may malfunctiondue to voltage noise.

In step S808, in order to confirm the results of step S805 which is donewith respect to the wiring which could be affected by voltage noise,i.e. the results of deleting or downsizing the initial dummy patternwhich adjoins the wiring which could be affected by voltage noise, astatic simulation is performed again using the inter-wiring parasiticcapacity data base DB7 and the wiring total parasitic capacity data baseDB8. In this static simulation, as in the case of the static simulationin step S803, the amount of voltage noise that each wiring imparts tothe adjacent wirings is calculated statically without using any testpattern. Then as mentioned before, on the basis of the results of thedynamic simulation and the static simulation, wiring information database DB9 is produced. This wiring information data base DB9 stores anode name, amount of voltage noise, etc. of the wirings which couldbecome malfunctional due to voltage noise.

In step S809, on the basis of the wiring information data base DB9generated through the dynamic simulation and the static simulation, itis to be determined whether the influence of voltage noise is canceledby deleting or downsizing the initial dummy pattern which adjoins thewiring which could be affected by voltage noise. If the influence ofvoltage noise is canceled, i.e. if the wiring information data base DB9does not store error information, the dummy pattern deleting/additionaldisposing process S800 should terminate. On the other hand, if theinfluence of voltage noise is not canceled, i.e. if the wiringinformation data base DB9 stores error information, step S810 is to beexecuted.

In step S810, the amounts of voltage noise are compared between thewiring information data base DB6 before the initial dummy pattern isdeleted or downsized in step 5805 and the wiring information data baseDB9 after the initial dummy pattern is deleted or downsized in stepS805, with respect to each wiring which could be affected by voltagenoise. If there is at least one wiring in which the amount of voltagenoise in the wiring information data base DB9 is more than the amount ofvoltage noise thereof in the wiring information data base DB6, step S811is to be executed with respect to every wiring of which amount ofvoltage noise is increased after step S805. On the other hand, if thereis no wiring in which the amount of voltage noise in the wiringinformation data base DB9 is more than the amount of voltage noisethereof in the wiring information data base DB6, step S600 (FIG. 4) orstep S700 (FIG. 10) is to be executed.

In step S811, wirings of which amount of voltage noise is increasedafter step S805, where the initial dummy pattern which adjoins thewiring which could be affected by voltage noise, are recovered to theinitial state. Then, step S600 (FIG. 4) or step S700 is to be executed.

In step 600 (FIG. 4) or in step S700 (FIG. 10), the additional insertionof dummy patterns considering the influence of voltage noise isperformed by a certain method which is described in the first or thesecond embodiment. The details of S600 and S700 are already described inthe first and second embodiments, and therefore, they will not bedescribed again for this case.

In the dummy pattern disposing method according to the third embodimentof the present invention, with respect to the wiring which could beaffected by voltage noise, first the process of deleting or downsizingthe initial dummy pattern which adjoins the wiring which could beaffected by voltage noise (step S805) is performed. Then, if theinfluence of voltage noise is not canceled after deleting or downsizingthe initial dummy pattern which adjoins the wiring which could beaffected by voltage noise, it is to be determined whether the influenceof voltage noise is decreased by deleting or downsizing this initialdummy pattern (step S810). If the influence of voltage noise isdecreased as a result of step S810, additional dummy patterns areinserted (step S600 or S700). On the other hand, if the influence ofvoltage noise is not decreased as a result of step S810, after thedeleted or downsized initial dummy patterns in step S805 are recoveredto the initial state (step S811), additional dummy patterns are inserted(step S600 or S700). With this processes, it is possible to reduce thenumber of additional dummy patterns based on the circumstance of voltagenoise, and therefore manufacturing cost can be decreased even more ascompared to the first and second embodiment.

Fourth Embodiment

In a method of disposing a dummy pattern according to a fourthembodiment of the present invention, a dummy pattern is disposed so thatconnection dividing capacitors, i.e. decoupling capacitors, are formedbetween power supply wirings.

FIGS. 17A and 17B are diagrams showing a portion of a wire structure ina semiconductor integrated circuit using a dummy pattern disposingmethod according to a fourth embodiment of the present invention. FIG.17A is a plan view of the wiring structure, and FIG. 17B is a sectionalview of the wiring structure taken along a line A-A′ shown in FIG. 17A.

In a semiconductor integrated circuit such as an application specificintegrated circuit, i.e. an ASIC, or the like, as shown in FIG. 17A, astructure where layers for power supply wirings and layers for signalwirings are alternately laminated is generally used. Moreover, wiringsformed in different layers, e.g. a VDD wiring 11 and a GND wiring 12shown in FIG. 17B, are arranged so that they may run at right angles toone another. In this structure, when it is viewed from the upperportion, a mesh structure is formed by a VDD wiring 11 and a GND wiring12. In this embodiment, in a signal wiring layer located between a powersupply wiring layer where the VDD wiring 11 is formed and a power supplywiring layer where the GND wiring 12 is formed, dummy pattern 13 isdisposed on the region corresponding to the crossover point where theVDD wiring 11 and the GND wiring 12 cross. With this structure where thedummy pattern 13 is disposed as mentioned above, since the effectiveinterval between the VDD wiring 11 and the GND wiring 12 becomessmaller, it is possible to form a decoupling capacitor which has a largecapacitance between the VDD wiring 11 and the GND wiring 12.

In the dummy pattern disposing method according to the fourth embodimentof the present invention, due to disposing the dummy pattern 13 betweenthe VDD wiring 11 and the GND wiring 12, it is possible to increase acapacitance between the power supply wirings. Thereby, it becomes easilyand simply possible to form the decoupling capacitor 14 which has alarge capacitance and stabilize a power supply voltage inside thesemiconductor integrated circuit.

This application claims priority to Japanese Patent Application No.2005-9626. The entire disclosures of Japanese Patent Application No.2005-9626 is hereby incorporated herein by reference.

While only selected embodiments have been chosen to illustrate thepresent invention, it will be apparent to those skilled in the art fromthis disclosure that various changes and modifications can be madeherein without departing from the scope of the invention as defined inthe appended claims. Furthermore, the foregoing descriptions of theembodiments according to the present invention are provided forillustration only, and not for the purpose of limiting the invention asdefined by the appended claims and their equivalents. Thus, the scope ofthe invention is not limited to the disclosed embodiments.

The term “configured” as used herein to describe a component, section orportion of a device includes hardware and/or software that isconstructed and/or programmed to carry out the desired function.

Moreover, terms that are expressed as “means-plus function” in theclaims should include any structure that can be utilized to carry outthe function of that portion of the present invention.

The terms of degree such as “substantially,” “about,” and“approximately” as used herein mean a reasonable amount of deviation ofthe modified term such that the end result is not significantly changed.For example, these terms can be construed as including a deviation of atleast ±5% of the modified term if this deviation would not negate themeaning of the word it modifies.

1-41. (canceled)
 42. A method of disposing a dummy pattern, which isused for a semiconductor integrated circuit having a multilevel wiringstructure in which a power supply wiring layer and a signal wiring layerare sequentially laminated, the method comprising the step of: disposinga dummy pattern on a region of the signal wiring layer that is adjacentto the power supply wiring layer, the power supply wiring layerincluding a first power supply wiring layer having a first power supplywiring extending toward a first direction, and a second power supplywiring layer having a second power supply wiring extending toward asecond direction which is perpendicular to the first direction, theregion corresponding to the crossover point where the first power supplywiring and the second power supply wiring cross over each other.
 43. Themethod of disposing a dummy pattern according to claim 42, wherein thepotential applied to the first power supply wiring differs from thepotential applied to the second power supply wiring.
 44. The method ofdisposing a dummy pattern according to claim 43, wherein the first powersupply wiring is a VDD wiring, and the second power supply wiring is aGND wiring.